bridgette_xc9500xl Project Status
Project File: | bridgette_xc9500xl.ise | Implementation State: | New
Module Name: | bridgette | Errors: |
Target Device: | xc95144xl-5TQ144 | Warnings: |
Product Version: | ISE 11.1 | Routing Results: |
Design Goal: | Balanced | Timing Constraints: |
Design Strategy: | Xilinx Default (unlocked) | Final Timing Score: |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report |  |  |  |  |
Translation Report |  |  |  |  |
CPLD Fitter Report (Text) |  |  |  |  |
Power Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
Post-Fit Simulation Model Report |  |

Date Generated: 04/10/2011 - 18:17:19